With developments of portable terminals, internet communication, etc., wireless communication has been receiving more and more increasing demands for the amounts of information and the communication speeds. As radio-frequency devices such as RF switches, miniaturization and integration technology has been increasingly adopted recently to substitute single devices, each of which have been made of a substrate such as an SOS (Silicon On Sapphire) substrate and a GaAs substrate, to a device that integrate these single devices onto an Si substrate. Particularly, methods for manufacturing radio-frequency devices by using SOI wafers have been largely extending a market.
As properties of radio-frequency devices, suppression of second harmonic and third harmonic have been a main requirement to prevent a crossed line of communication. To fulfil this requirement, the substrate have to be an insulator. In SOI wafers, enlargement of a buried oxide film (BOX layer) thickness can be conceived as one of the measure. Oxide films, however, has lower thermal conductivity, and cannot remove the generated heat in operating radio-frequency devices. Accordingly, the use of a higher resistance Si substrate was devised as the support substrate of an SOI wafer. This can suppress electrical conduction under the BOX layer, and can suppress harmonic of the radio-frequency devices. When the SOI layer is electrically charged, however, a depletion layer is generated on the surface of the Si substrate immediately under the BOX layer to form an inversion layer. At this portion, electric conduction is generated to make it impossible to control harmonics. One of the method to solve this problem is to provide a carrier trap layer immediately under the BOX layer (e.g., see Patent Documents 1 to 3).
As the carrier trap layer, polycrystalline silicon layers are most widespread. The polycrystalline silicon layer traps carriers at the grain boundary to suppress electric conduction.
As a method to provide the polycrystalline silicon layer, an SOI wafer provided with a polycrystalline silicon layer can be manufactured by laminating a polycrystalline silicon layer onto a wafer for a support substrate (a base wafer), and then bonding this to a wafer having an oxide film (a bond wafer). In order to realize bonding of wafers in this process, however, the polycrystalline silicon layer surface has to be flat, and it has been devised to perform bonding after removing the surface roughness by polishing.
In manufacturing of a conventional mirror polished silicon single crystal wafer (hereinafter, referred to as a PW) that is used for device production and so on, a silicon single crystal ingot is grown by a Czochralski method, for example. This ingot is processed by slicing off thin disks, and the disk is subjected to various processes such as chamfering, lapping, etching, and polishing to prepare a mirror-plane form wafer (a mirror polished wafer).
In a polishing process of a silicon wafer, the polishing is generally performed through plural stages from rough polishing to finish polishing. For example, primary polishing is performed with a polishing stock removal of about several μm to remove deformation to flatten the wafer surface after a lapping process or an etching process. Subsequently, secondary polishing is performed with a polishing stock removal of about 1 μm to remove scratches formed at the primary polishing and to improve the surface roughness. Furthermore, finish polishing is performed with a polishing stock removal of less than 1 μm to make a haze-free surface. In this way, a wafer surface is mirror polished through rough polishing (primary polishing and secondary polishing) and finish polishing (e.g., see paragraph (0004) in Patent Document 4).
The polishing is performed by setting conditions so as to make the flatness of the polished mirror portion and the surface roughness of the polished mirror portion have smaller values in each stage while moderating the polishing conditions in each and every time of this polishing by changing the size of polishing abrasive grains to be finer and lowering the hardness of the polishing cloth, for example (e.g., see paragraph (0027) in Patent Document 5).
Particularly, a silicon wafer with the diameter of 300 mm is subjected to primary polishing by double-side polishing to satisfy the severe specifications of the flatness, followed by secondary and finish polishing by single-side surface polishing to improve the surface having scratches and the surface roughness (e.g., see paragraph (0002) in Patent Document 6).